1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to interconnection mechanisms implemented on integrated circuits.
2. Description of the Related Art
The effort to increase the amount of computing power on a single integrated circuit (IC) die has, in recent years, led to the design and manufacture of multi-core processors. A multi-core processor effectively implements two or more processors on a single IC die by providing two or more respective processing cores. Each of the cores may include dedicated cache memories and other circuitry. However, some cache memories may be shared among the cores. Similarly, input/output (I/O) interfaces and other circuitry may also be shared among the cores. System level random access memory (RAM) may also be shared by the cores of a multi-core processor.
For various reasons (e.g., maintaining cache coherency, performing parallel computing tasks, etc.), there may be a need at times for communications between the various agents (e.g., cores, cache memories, I/O interfaces) of a multi-core processor. In order to support such communications, an on-chip network or a crossbar may be provided.
An on-die network may be used to connect every agent on the IC die to every other agent. Such an approach may provide efficient communications between a given pair of agents. However, on-die networks may require a significant amount of die area, which can limit the number of agents that may be implemented. Furthermore, communications latencies may vary between one set of agents and another, thus impacting performance. Collisions are another factor that may mitigate the performance of an on-die network.
A crossbar may provide a known, consistent latency for communications between any two sets of agents. Crossbars may connect a group of signal lines forming a bus to another group of signal lines forming another bus. A typical crossbar may include inputs from a number of different buses and outputs to a number of different buses. Crossbars may be capable of connecting any one bus to any other bus or to selected ones of the other buses. However, crossbars may be subject severe wire congestion due to a number of different buses being multiplexed in close vicinity to each other. Furthermore, the number of interconnections in close proximity can, at times, give rise to noise issues.
Thus, in implementing an IC (such as a multi-core processor) requiring communications among a number of different agents, the factors discussed above may be considered. For example, if variable latency is not an issue, an on-die network may be implemented. If latency is an issue but sufficient area is available such that wire congestion is minimized, a crossbar may be considered.